When TSMC reported second-quarter results on July 16, 2026, it did something it had not done in any prior quarter: it listed 2-nanometer in the revenue-by-technology table.
That is worth pausing on, because one quarter earlier the node was not there at all. The April 16 release broke out 3nm at 25%, 5nm at 36% and 7nm at 13% of wafer revenue — 2nm did not appear as a line item. Three months later it was 3%.
The same earnings call carried two other signals. Chairman and CEO C.C. Wei raised the full-year outlook, saying the company now expects 2026 revenue growth to be “slightly above 40% year over year in US dollar terms.” And CFO Wendell Huang guided third-quarter gross margin down 1.7 percentage points at the midpoint, because the steep ramp of 2nm is expected to dilute gross margin by about 3 to 4 percentage points.
Read together those three facts look contradictory: the most advanced node finally starts selling, the year gets better, and margins go down. Most coverage compresses this into “2nm drags on margins” and stops there. The more useful takeaway is a framework you can reuse every time a foundry brings up a node: the profit curve of a leading-edge process is J-shaped, an early ramp compressing margin is the norm — and the explanation people reach for first, that yield has not come up yet, is precisely the one TSMC’s own statements contradict.
Pin the numbers down first
Everything below comes from TSMC’s own releases and call transcripts, not from secondary coverage.
Second-quarter consolidated revenue was NT$1,270.38 billion (US$40.20 billion), up 36.0% year over year and 12.0% sequentially. Net income was NT$706.56 billion and diluted EPS NT$27.25, both up 77.4% year over year. Gross margin was 67.7%, up 1.5 points from 66.2% in Q1; operating margin 60.3%, net margin 55.6%.
By technology: 2nm 3%, 3nm 30%, 5nm 33%, 7nm 11%. Everything at 7nm and below made up 77% of wafer revenue, against 74% the prior quarter. HPC grew 20% sequentially to 66% of total revenue.
Third-quarter guidance: revenue of US$44.6-45.8 billion, up 12% sequentially and 37% year over year at the midpoint; at an assumed rate of US$1 to NT$32, gross margin of 65% to 67% and operating margin of 56% to 58%.
Two figures from this call get conflated constantly, so separate them now:
- The “3 to 4 percentage points” is the 2nm ramp’s effect on second-half gross margin. Huang’s wording was explicitly “in the second half of the year” — not the full year.
- The “2% to 3%” is overseas fab dilution, an estimate for the early stages of the next several years, widening to 3% to 4% in the later stages. It has nothing to do with 2nm.
Every dilution figure in this article refers to the first unless stated otherwise.
Why a hot node compresses margin
Depreciation: five-year schedule, multi-year revenue ramp
This is the hardest part of the mechanism, and TSMC spells it out in its own accounting notes: machinery and equipment is depreciated straight-line over five years (buildings over 10 to 20 years).
So the moment a 2nm tool is accepted, it starts generating a fixed monthly charge for five years regardless of how many wafers cross it, what the yield is, or what the customer pays. Revenue does not work that way. A new node typically needs several quarters to climb into double-digit revenue share. Cost arrives as a step function; revenue arrives as a ramp. The gap between the two is the dilution.
That is not an abstraction — it is visible in this quarter’s cash flow statement. Depreciation and amortization was NT$198.54 billion in Q2 against NT$165.45 billion in Q1, a 20.0% increase in a single quarter, while revenue grew 12.0%. When the cost line outruns the revenue line, margin compresses. There is no third possibility.
Capital expenditure was NT$496.00 billion (US$15.7 billion) in Q2 versus NT$350.76 billion in Q1. Today’s capex becomes the next five years of depreciation, and TSMC has raised its 2026 capital budget to US$60-64 billion, with 70-80% going to advanced process technologies. That number tells you two things, not one: the company is confident, and the depreciation base will keep stepping up.
Work in progress: seven more days of inventory
Inventory days rose seven days to 87 in the second quarter, and TSMC’s stated reason was one clause: primarily the ramp of N2.
A node in early ramp carries more work in progress than a mature one. Those wafers have already absorbed cost but cannot yet be recognised as revenue. It is a second, independent form of cost arriving early — depreciation sits on the balance sheet, WIP sits on the production line.
Better unit economics, and margin still goes down
First, something usually assumed rather than checked: TSMC does not publish wafer pricing by node, so how much N2 sells for relative to N3 is not verifiable from outside, and this article does not assume it.
What the company has said is this. Asked in October 2025 about the scale of 2nm dilution, CFO Wendell Huang answered: “N2’s structure profitability is better than N3.” That sharpens the question rather than answering it — if the unit economics are better, why does the blended margin still fall?
The answer is weighting. Margin is a weighted average, and here the weights dominate.
2nm was 3% of wafer revenue. Even if its per-wafer margin matched the corporate average exactly, it would move the blended number by 3% of the way. Meanwhile, producing that 3% requires carrying the full depreciation, full facilities cost and full headcount of an entire 2nm line. Three percent of the numerator against one hundred percent of the capacity cost — that is where the dilution comes from arithmetically.
There is also a pricing constraint people underrate. Asked about wafer pricing strategy on the same call, Wei said the higher the margin the better, of course, but that TSMC is a partner and does not want to squeeze customers out of their markets; the company will not suddenly raise prices fourfold or fivefold, but earns its value and keeps profit sufficient to fund long-term expansion. He added, jokingly, that he envies memory makers’ 86% gross margin.
That quote discloses no price level, but it does disclose a cadence: pricing adjustments are gradual and negotiated, while depreciation is automatic and prescribed by accounting standards.
So what about “yield has not come up yet”?
That is the explanation most people reach for, and it is the one TSMC’s own statements contradict.
On the October 2025 call the company said N2 was on track for volume production “with good yield,” and on the same call the CFO said N2’s structural profitability is better than N3’s. Neither yield nor unit economics is moving the wrong way.
Here the claim has to stop at exactly the right place. TSMC has never decomposed those 3 to 4 points into “so much depreciation, so much yield, so much utilisation.” The company lists six factors that determine profitability and then gives a single combined figure. So the defensible conclusions are:
- it can be said that “yield is the problem” does not square with the company’s own statements;
- it can be said that the lag between depreciation and the revenue ramp is a factor TSMC itself names repeatedly — in 2024 for N3, and again now for N2;
- it cannot be said that the dilution comes only from that lag, or what share of it does. Nobody has published that split, and it is not recoverable from outside.
The distinction still changes how you read next quarter: treating this as a process failure and treating it as an investment period with a precedent and a known duration lead to opposite conclusions.
The counterexample: N3 was flagged with the same 3 to 4 points two and a half years ago
The best way to judge whether this dilution is a problem is to look at the last time it happened.
On the fourth-quarter call of January 18, 2024, Huang said almost exactly the same thing: Q4 2023 gross margin fell 130 basis points sequentially to 53.0%, primarily on dilution from the continued 3nm ramp, and N3 was expected to dilute gross margin by about 3 to 4 percentage points for the full year of 2024. He also guided 2024 depreciation up close to 30% year over year, mainly on the 3nm ramp. The company’s long-term margin language at the time was “53% and higher is achievable.”
Two and a half years later, 3nm is 30% of wafer revenue and the company posted a 67.7% quarterly gross margin.
First, a subtraction that is easy to get wrong
Seeing “dilutes gross margin by 3 to 4 percentage points,” the instinct is to subtract it from the reported number: 67.7% − 3.5% ≈ 64.2%. That subtraction is wrong, and it is wrong conceptually rather than arithmetically.
Dilution measures the gap against a counterfactual — what margin would have been without the ramp. Nobody publishes that number and it cannot be reconstructed from public data. It is not a decline measured from last quarter’s reported margin. By the same logic, the 53.0% printed for Q4 2023 was already a post-dilution result (the release says the 130-basis-point sequential drop was primarily the N3 ramp), so subtracting another 3 to 4 points from it double-counts.
The two moments can therefore only be compared using like for like. TSMC has published two such sets:
- The N3 round: reported margin 53.0% (2023 Q4); next-quarter guidance 52%-54% (2024 Q1, 53% midpoint); ramp dilution flagged at about 3-4 points for full-year 2024.
- The N2 round: reported margin 67.7% (2026 Q2); next-quarter guidance 65%-67% (2026 Q3, 66% midpoint); ramp dilution flagged at about 3-4 points for the second half of 2026.
The same flagged magnitude, occurring at margin levels 14.7 points apart. One point of margin is 1.9% of the 53.0% level and 1.5% of the 67.7% level — the same headline number carries different weight at each. That is the only form in which this comparison holds.
Two honest limitations belong here rather than in a footnote. First, the periods are not the same scope: N3’s 3-to-4 points covered full-year 2024, N2’s covers the second half of 2026, and absorbing the same magnitude in half the time is the denser compression. Second, the two quarters sit at different points of their ramps: by Q4 2023 N3 was already 15% of wafer revenue with dilution well underway, whereas N2 was 3% in Q2 2026 with the company explicitly placing the heavy dilution in the second half. So 53.0% is a mid-ramp level and 67.7% is closer to a start-of-ramp level. Both caveats distort the comparison.
Huang also made a point in October 2025 worth carrying forward: the old habit of asking how many quarters a new node needs to reach the corporate average has lost much of its meaning, because the corporate average itself keeps moving up. Chasing a moving benchmark produces a moving answer.
Planned dilution versus deteriorating profitability
Both look identical on the income statement — gross margin goes down — and they mean opposite things. Three questions separate them.
First: was the decline announced in advance or explained afterwards? Planned dilution appears in guidance, is quantified as a range, and is scoped to a period. Deteriorating profitability shows up as a miss against the company’s own guidance and gets explained on the following call. Here, the 3-to-4 points came from the CFO while giving guidance.
Second: is the revenue outlook moving the same way? Margin guidance went down while the full-year growth outlook went up past 40%, capex was raised to US$60-64 billion, and the dividend went from NT$18 per share in 2025 to NT$24 in 2026. Demand problems do not look like that.
Third: did the previous node’s dilution actually converge? This is the load-bearing test. In October 2025 Huang said N3 dilution was gradually coming down and that N3 was expected to reach the corporate average sometime in 2026. N3 delivered 30% of wafer revenue this quarter while company margin hit a recent high. The last node’s dilution did converge the way the company said it would — and that, not the company’s own characterisation, is the only real evidence that “planned” means anything.
Conversely: if dilution ever overshoots its own guidance, the revenue outlook is cut at the same time, and the previous node’s dilution refuses to converge, then all three conditions point at genuine deterioration.
Taiwan angle: Fab 20, Fab 22 and thirteen more
For Taiwan, 2nm is not an abstract industry story. It has addresses.
TSMC’s official 2nm technology page states plainly that Fab 20 and Fab 22 are the 2nm production facilities. On the October 2025 call, Wei said the company was preparing multiple phases of 2nm fabs in both the Hsinchu and Kaohsiung Science Parks with the support of the Taiwan government. On this quarter’s call he added that TSMC is building 13 leading-edge and advanced packaging fabs in Taiwan over the next several years and will continue to invest there.
Connect those to the capital budget and the local consequence becomes concrete. Of the US$60-64 billion planned for 2026, 70-80% goes to advanced process and roughly 10-20% to advanced packaging, testing and mask making. A meaningful share of that lands on facility engineering, cleanrooms, electrical and mechanical work, gases and chemicals, specialty piping, facility operations and tool install — the parts of the supply chain that never make headlines but do book revenue in Taiwan. Which is the point worth holding onto: “margin dilution” and “Taiwanese suppliers booking orders” are the same money viewed from two sides. On the income statement it is called depreciation.
The evidence limit here should be explicit: TSMC does not disclose how capex splits between Taiwan and overseas, nor does it publish a supplier list. The paragraph above is a directional inference from the budget, the stated allocation and the fab count — not a quantified order forecast.
Some of that 2nm output is already in real products. AMD announced in May 2026 that its sixth-generation EPYC, codenamed Venice, had entered production ramp on TSMC’s 2nm process in Taiwan — a thread I pulled on in the AM5 upgrade cost analysis. It remains one of the few officially confirmed high-performance products running on N2.
When consumers meet 2nm, and what it does to prices
TSMC never names customers, so any claim about which phone ships 2nm first is inference. But two official statements sketch the outline: N2 entered volume production in Q4 2025 as planned, and the company expects a faster ramp in 2026 driven by both smartphone and HPC/AI applications.
Smartphones being one of the two stated drivers, with volume production more than half a year old, the reasonable inference is that the flagship cycles from late 2026 into the first half of 2027 are where 2nm shows up in consumer devices at scale. That is an inference from official statements, not a schedule TSMC has published.
As for pricing, the intuitive model is wrong. Wafer cost does not pass through proportionally, because the SoC is one line in a bill of materials and retail pricing also absorbs brand strategy, channel, currency and marketing. More to the point, by Wei’s own description of pricing philosophy, wafer increases are gradual and negotiated rather than stepped. The realistic expectation is that leading-edge cost pressure shows up as slower spec upgrades at a given price point, or a slow upward creep in flagship price bands — not as one generation suddenly jumping.
On the technology itself, TSMC’s April 2023 symposium release put numbers on N2: relative to N3E, up to 15% speed improvement at the same power, or up to 30% power reduction at the same speed, with greater than 1.15x chip density. Three qualifiers travel with those figures: “up to” rather than “about,” the baseline is N3E rather than N3, and the claim dates from two years before volume production. N2 uses TSMC’s first-generation nanosheet transistors; the N2P extension is scheduled for volume production in the second half of 2026.
Four numbers I will be watching
1. Next quarter’s 2nm revenue share. It is in the first paragraph of every quarterly release; no analyst report required. The slope from 3% upward determines how long the bottom of the J-curve lasts. The comparison is already on the record: N3 was 6% of wafer revenue for full-year 2023, 15% in Q4 2023, 23% in Q3 2025 and 30% this quarter. Single digits to thirty percent took about three years.
2. Where Q3 actually lands inside the 65-67% guided range, and whether Q4 guidance stabilises. The upper end means the dilution is being absorbed better than planned. Below 65% is the number that would justify revisiting the thesis.
3. The sequential growth rate of depreciation and amortization. It was 20.0% this quarter. When that starts flattening, the cost step is finished — and it typically leads the margin recovery. It sits on the second line of the cash flow statement in the management report and never makes a headline.
4. The exchange rate. Huang gave a genuinely useful conversion: every 1% move in the US dollar against the NT dollar affects gross margin by about 40 basis points. Q3 guidance assumes US$1 to NT$32. Subtract the currency component before reading anything into a margin move, or you will mistake FX noise for a verdict on 2nm.
Back to the apparent contradiction. 2nm dilutes margin as it heats up not because it fails to make money, but because its costs are recognised in full before its revenue has meaningfully started. That was true of N3 once, and of N5 and N7 before it. The number to track was never how many points came off this quarter — it is whether the curve turns back up on schedule, the way the last one did.
Data verified 2026-08-06. All financial figures are taken from TSMC’s own filings, not from secondary coverage. Sources: TSMC second quarter 2026 earnings release (2026-07-16; 2nm at 3% of wafer revenue, 67.7% gross margin), TSMC 2Q26 earnings conference transcript (3-4 point 2H dilution, full-year outlook above 40%, US$60-64bn capital budget, 13 fabs in Taiwan), TSMC 2Q26 management report (depreciation and capex cash flow detail), TSMC first quarter 2026 earnings release (2026-04-16; no 2nm line item, 66.2% gross margin), TSMC 4Q23 earnings conference transcript (2024-01-18; N3 diluting full-year 2024 margin by 3-4 points, 53.0% gross margin, depreciation up close to 30%), TSMC 3Q25 earnings conference transcript (N2 good yield, structural profitability better than N3, Hsinchu and Kaohsiung 2nm phases, 40bp margin sensitivity per 1% FX move), TSMC official 2nm technology page (4Q25 volume production, first-generation nanosheet, Fab 20 and Fab 22 as the 2nm facilities, N2P in 2H26), TSMC 2023 Technology Symposium release (2023-04-27; N2 up to 15% speed, up to 30% power, greater than 1.15x density versus N3E), TSMC 2023Q4 financial statement notes (machinery and equipment straight-line over 5 years, buildings 10 to 20 years).